Lab and Coral NameNANO / RTA-900C
ModelAG Associates Heatpulse 410
SpecialistEric Lim    (Kurt Broderick)
Physical Location4U
Process CategoryDiffusion
Material KeywordsSiO2, SiNx, Dielectrics, CMOS Metals, Non-CMOS Metals, Non-Standard Materials
Sample Size4" Wafers, Pieces
AlternativeNANO / Anneal-Tube
Keywordssingle wafer, manual load, multiple pieces, top side of sample, vacuum, temperature, manual operation
The RTA allows for short anneals with fast temperature ramps in N2, O2, or N2/H2 ambients. Samples are manually placed on a 4" handle Si wafer. Sample temperature is indirectly measured by a TC connected to the handle wafer. Gas ambient is controlled manually by the user. Time and temperature parameter values are entered before each run.

Best forAnnealing in controlled ambient
LimitationsSample temperature varies by ~30C across the handle wafer.
Characteristics/FOMTemperature range: 400-900C, time range: 0-300 seconds.
Caution withEven after purging the chamber with only N2, the ambient will never be completely free of oxygen.
Machine Charges (academic rate)4pu/wafer
Process Matrix Details

Been in the ALDSamples that have been in any of the ALD systems
Pyrex SubstratesPyrex substrates can be a concern due to high sodium content, which contaminates CMOS frontend tools
III-V SubstratesAny III-V substrates, e.g. GaAs, GaN, InP, and so on. Note though that many common III-V substrates will also carry the Au flag, but there are some GREEN III-V substrates.
Germanium on surfaceSamples with germanium on the surface (typically grown films)
Germanium buriedSamples with germanium buried below a different film
PiecesWafer pieces may not be handled by the equipment, and are harder to thoroughly clean - preventing them from running in certain tools.
Gold or RED color codeRED color code substrates. These are gold-contaminated or have been processed in gold contaminated tools. Gold and other metals can contaminate silicon devices (GREEN color code) and have to be separated.
Any exposure to CMOS metalIf the sample had ever seen a CMOS metal (or a tool that accepts CMOS metal), then some frontend tools could be contaminated by this.
CMOS metal on surfaceCMOS compatible metals exposed on the surface. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
CMOS metal buriedCMOS compatible metals covered entirely by a different material. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
Been in the STS DRIEThe DRIE etch leaves behind polymer residues on the sidewall ripples, which can be a contamination concern for some tools.
Been in the SEMA sample viewed in the SEM must have used the appropriate chuck to avoid cross-contamination
Been in the Concept1The Concep1 deposits dielectrics on GREEN wafers, however it also accepts metal and there can be cross-contamination for diffusion area
Has PhotoresistSamples with photoresist cannot be exposed to high temperatures, which is typical in deposition tools. Outgassing can be a concern.
Has PolyimidePolyimide is a very chemically resistant polymer, and can tolerate higher temperatures but cannot be exposed to typical PECVD deposition temperatures or diffusion furnaces. Outgassing can be a concern.
Has Cured SU8Not fully cured SU8 residues can heavily contaminated plasma chambers or destroy other user's samples, but fully cured SU8 is permitted in certain tools.
Coming from KOHAfter a KOH etch, the samples must receive a special clean because the K ions are highly contaminating to CMOS frontend tools
Coming from CMPAfter a CMP, the samples must receive a special clean, because the slurry residues otherwise introduce contamination and particles.

Not Allowed
Ever been in EMLSamples from EML are never permitted to return to ICL or TRL

For more details or help, please consult PTC matrix, email, or ask the research specialist (Eric Lim)